1. Technical Field
The present invention relates to semiconductor memory circuits, and more particularly, to a non-volatile semiconductor memory circuit of which a write operation is improved, and a method of controlling the same.
2. Related Art
In general, a unit cell of a phase change random access memory (hereinafter, referred to as PCRAM) includes one switching element connected to a word line (for example, a diode) and one variable resistor, such as a GST (Germanium Antimony Telluride GexSbyTez) variable resistor connected to a bit line. The PCRAM can store data in a memory cell by controlling a reversible phase change of the variable resistor GST using an electric pulse.
For example, when a pulse current is applied to a memory cell for a predetermined time, the state of the variable resistor GST can be changed into an amorphous state which can be assigned to a logical reset state). When a pulse current is applied for a longer time than the predetermined time, the state of the variable resistor GST can be changed into a crystalline state which can be assigned to a logical set state.
The amorphous state of the variable resistor GST is not an immediately stabilized state. It exhibits an intrinsic kinetic physical characteristic which is thought to be brought about by relatively slow solid state reorganization mechanisms that are driven by the diffusion of the excess imposed Joule heat. A representative example of this intrinsic kinetic physical characteristic can be seen as a resistance drift as a function of time. The resistance drift refers to a phenomenon in which the resistance of the variable resistor GST increases with time due to various causes. The resistance drift may occur more markedly as the resistance of a material is higher. That is, in the high-resistance state of the variable resistor GST which corresponds to the reset state, the resistance drift becomes markedly more noticeable.
In particular a problem can arise in which a verify read operation for a write operation is performed at an earlier timing than that of a normal read operation. In other words, verification is performed at a point of time when a difference in resistance seems to be large from the resistance of actual target data during the verify read operation. Therefore, it may be difficult to perform correct data determination.